The present invention relates generally to a automatic cell placing method and, more particularly, to an automatic cell placing method of two-dimensionally arraying cells in a placing design of a semiconductor device according to a standard cell system.
The standard cell system placing method has hitherto been employed in the placing design of a semiconductor integrated circuit.
FIG. 17 is a layout diagram illustrating a semiconductor device which has been designed employing a standard cell system placing method.
According to this method, to start with, logic circuit/logic blocks are optimally designed by combining basic logic circuits to have high performance with minimum occupied area. Then they are registered as standard cells in a computer. Then, when designing a semiconductor device, a variety of standard cells registered are selected and combined, thereby making a cell placing design. As illustrated in FIG. 17, desired cells 141, 142, etc. are arranged in a plurality of rows on the semiconductor integrated circuit including external terminals 145, 146, etc., and a cell placing, a cell row interval and a wiring pattern are determined to minimize a total sum of wire lengths of wires, 143, 144, etc. for connecting the respective cells to the external terminals.
A minimum-cut method is known as a typical algorithm for the cell placing, etc. (See I. Bhandari et al. "The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-Cut Placement" 25th ACM/IEE Design Automation Conference, Paper 41.6, pp. 681-685, 1988 IEEE, etc.). According to this minimum-cut method, a two-dimensional coordinate placing of the cells involves dividing large cell groups, minimizing the number of connection nets between the divided cell groups, thereafter sequentially subdividing the cell groups, then minimizing the number of connection nets between these subdivided cell groups, and repeating such operations.
In the above-described minimum-cut method, however, an emphasis is put on the number of nets (signal lines) for connecting the cells to clusters, and therefore a difference in terms of length among wires is easy to occur. Further, if large and small basic cells are intermingled, there tends to be a bias in a distribution of connecting terminals as a whole as in the case of a concentration of the small cells.
This being the case, what is described above might lead to an increase in chip size of the whole, which might therefore bring about a rise in production costs. Moreover, since it is difficult to meet a requirement for circuit operation timing necessary for the circuit operation, there are caused increases both in design costs and in design period due to repetitive design works.